1. Field of the Invention
This invention relates to multiprocessor computer architectures and, more specifically, to the handling and processing of interrupts by multiprocessor computer systems.
2. Background Information
Distributed shared memory computer systems, such as symmetrical multiprocessor (SMP) systems, support high performance application processing. Conventional SMP systems include a plurality of processors coupled together by a bus. One characteristic of SMP systems is that memory space is typically shared among all of the processors. That is, each processor accesses programs and data in the shared memory, and processors communicate with each other via that memory (e.g., through messages and status information left in shared address spaces). In some SMP systems, the processors may also be able to exchange signals directly. One or more operating systems are typically stored in the shared memory. These operating systems control the distribution of processes or threads among the various processors. The operating system kernels may execute on any processor, and may even execute in parallel. By allowing many different processors to execute different processes or threads simultaneously, the execution speed of a given application may be greatly increased.
During operation, entities or “agents” of the computer system often generate interrupt signals in response to a need for service or the detection of an error by those entities or agents, which may include processors, memory controllers, inputloutput (I/O) devices, etc. For example, when an I/O device requests some particular type of service or action from a processor, it often signals the processor by issuing an interrupt. Specifically, the I/O device may assert an interrupt input pin of either the processor or an interrupt controller, which forwards the interrupt to the processor. Provided the interrupt is permitted, it will be acknowledged by the processor at the end of the current processor cycle. The processor then services the interrupt typically by branching to a special service routine written to handle that particular interrupt. Upon servicing the interrupt, the processor signals the I/O device that it completed the interrupt, typically with a write to the device, and the I/O device deasserts the interrupt signal. The processor then signals to the interrupt controller that the interrupt event has been serviced, typically with an end of interrupt signal.
Multiprocessor, distributed memory systems may have many I/O devices generating large numbers of interrupts. The Peripheral Component Interface (PCI) specification standard, for example, defines four level sensitive interrupts (INTA, INTB, INTC and INTD) that can be generated by a single, multifunction, I/O device. In many computer systems, the number of interrupts that can be supported is limited. As a result, a given interrupt signal, especially a level sensitive interrupt (LSI), may be shared by more than one I/O device. If two devices are asserting a given LSI, it will remain asserted until both devices have been serviced.
The process of collecting interrupts and sending them to the processors for servicing can be complex. Inefficient processing of interrupts can result in reduced efficiency of the system. For example, in some implementations, it is possible for the end of interrupt to be detected prior to the I/O device deasserting the interrupt signal. This may cause the system to believe the interrupt signal has been asserted a second time even though there is no work to be done. Because interrupt signals can be shared, it is not sufficient simply to wait for the interrupt signal to be deasserted as a second interrupt may be signaled immediately after the first and/or may overlap with the prior interrupt, resulting in a continuously asserted interrupt signal. The occurrence of interrupt signaling when no service is actually requested is known as “passive release”, and reduces the efficiency of the computer system. However, Prior art computer systems were built to expect and tolerate the passive release of interrupts, even though this would result in degraded system performance. Accordingly, a need exists for efficiently collecting and processing interrupts in large, multiprocessor computer systems.